All Materials regarding to B.tech R-20 in Electronics and communication Engineering with unit wise for Every Subjects are available.
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| ECE 2-2 DICD | ||
|---|---|---|
| S.No | Chapters / Units | Download Link |
| 1 | Unit 1 | Download |
| 2 | Unit 2 | Download |
| 3 | Unit 3 | Download |
| 4 | Unit 4 | Download |
| 5 | Unit 5 | Download |
ECE 2-2 DICD Important Questions and Topics Unit Wise
UNIT-I
Hardware Description Languages.
VHDL: Introduction to VHDL, entity declaration, architecture, data-flow, behavioral and structural style
ofmodelings,datatypes,dataobjects,configurationdeclaration,package,generic,operatorsandidentifiers,PROCE
SS,IF, CASE & LOOPstatements, VHDL libraries.
Verilog HDL: Introduction to Verilog HDL, data types, data operators,module statement, wire statement, if-
elsestatement, case-endcasestatement,Verilog syntax and semantics(qualitative approach)
UNIT-II
Combinational Logic Design: Parallel binary adder, carry look ahead adder, BCD adder, Multiplexers
anddemultiplexers and their use in combinational logic design, ALU, digital comparators, parity generators,
codeconverters, priority encoders. (Qualitative approach of designing and modeling the mentioned
combinationallogiccircuits with relevant digital ICs using HDL)
UNIT-III
Sequential Logic Design: Registers, applications of shift registers, ripple or a synchronous counters,
synchronous counters, synchronous and a synchronous sequential circuits, hazards in sequential circuits.
(Qualitative approach of designing and modeling the mentioned sequential logic circuits with relevant digital
ICs using HDL)
UNIT-IV
Combinational MOS Logic Circuits: Introduction, MOS logic circuits with depletion nMOS loads: two-
inputNOR gate, generalized NOR structure with multiple inputs, transient analysis of NOR gate, two-input
NANDgate, generalized NAND structure with multiple inputs, transient analysis of NAND gate, CMOS
logic circuits:CMOS NOR2 gate, CMOS NAND2 gate,complex logic circuits, complex CMOS logic gates,
AOI and OAIgates, Pseudo-nMOS gates, CMOS full-adder circuit,CMOS transmission gates (Pass Gates),
complementarypass-transistorlogic.
UNIT-V
Sequential MOS Logic Circuits: Introduction, behavior bistable elements, SR latch circuit, clocked latch
andflip-flop circuits: clocked SR latch, clocked JK latch, master-slave flip-flop, CMOS D-latch and Edge-
triggeredflip-flop,Schmitt trigger circuit, basic principlesof pass transistor circuits.
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