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| ECE 3&2 VLSI DESIGN | ||
|---|---|---|
| S.No | Chapters / Units | Download Link |
| 1 | Unit 1 | Download |
| 2 | Unit 2 | Download |
| 3 | Unit 3 | Download |
| 4 | Unit 4 | Download |
| 5 | Unit 5&6 | Download/ Download |
ECE 3-2 VLSI DESIGN Important Topics
UNIT-I:
INTRODUCTIONANDBASICELECTRICALPROPERTIESOFMOSCIRCUITS:
VLSI Design Flow, Introduction to IC technology, Fabrication process: nMOS, pMOS and
CMOS. Ids versus Vds Relationships, Aspects of MOS transistor Threshold Voltage, MOS
transistor Trans, Output Conductance and Figure of Merit. nMOS Inverter, Pull-up to Pull-
down Ratio for nMOS inverter driven by another nMOS inverter, and through one or more
pass transistors. Alternative forms of pull-up, The CMOS Inverter, Latch-up in CMOS
circuits, Bi-CMOS Inverter, Comparison between CMOS and BiCMOS technology, MOS
Layers, Stick Diagrams, Design Rules and Layout, Layout Diagrams for MOS circuits
UNIT-II:
BASIC CIRCUIT CONCEPTS: Sheet Resistance, Sheet Resistance concept applied to
MOS transistors and Inverters, Area Capacitance of Layers, Standard unit of capacitance,
some area Capacitance Calculations, The Delay Unit, Inverter Delays, driving large
capacitive loads, Propagation Delays, Wiring Capacitances, Choice of layers.
SCALING OF MOS CIRCUITS: Scaling models and scaling factors, Scaling factors for
device parameters, Limitations of scaling, Limits due to sub threshold currents, Limits on
logic levels and supply voltage due to noise and current density. Switch logic, Gate logic.
UNIT-III:
BASIC BUILDING BLOCKS OF ANALOG IC DESIGN: Regions of operation of
MOSFET, Modelling of transistor, body bias effect, biasing styles, single stage amplifier
with resistive load, single stage amplifier with diode connected load, Common Source
amplifier, Common Drain amplifier, Common Gate amplifier, current sources and sinks.
UNIT-IV:
CMOS COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUIT DESIGN:
Static CMOS Design: Complementary CMOS, Rationed Logic, Pass-Transistor Logic.
Dynamic CMOS Design: Dynamic Logic-Basic Principles, Speed and Power Dissipation
of Dynamic Logic, Issues in Dynamic Design, Cascading Dynamic Gates, Choosing a Logic
Style, Gate Design in the Ultra Deep-Submicron Era, Latch Versus Register, Latch based
design, timing decimation, positive feedback, in stability, Meta stability, multiplexer based
latches, Master-Slave Based Edge Triggered Register, clock to q delay, setup time, hold
time, reduced clock load master slave registers, Clocked CMOS register. Cross coupled
NAND and NOR, SR Master Slave register, Storage mechanism, pipelining.
UNIT-V:
FPGA DESIGN: FPGA design flow, Basic FPGA architecture, FPGA Technologies,
Introduction to FPGA Families.
INTRODUCTIONTOADVANCEDTECHNOLOGIES: Giga-scale dilemma, Short
channel effects, High–k, Metal Gate Technology, Fin-FET, TFET.
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