All Materials regarding to B.tech R-20 in Electrical and Electronics Engineering 3rd Year 2nd Semester with unit wise for Every Subjects are available.
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| EEE 3-2 MPMC | ||
|---|---|---|
| S.No | Chapters / Units | Download Link |
| 1 | Unit 1 | Download |
| 2 | Unit 2 | Download |
| 3 | Unit 3 | Download |
| 4 | Unit 4 | Download |
| 5 | Unit 5 | Download |
EEE 3-2 MPMC Important Topics Questions
UNIT - I
Review of Number Systems & Codes:
Representation of numbers of different radix, conversion from one radix to another radix, r-
1’s complements and r’s complements of signed members. Gray code,4 bit codes; BCD,
Excess-3, 2421, 84-2-1 code etc., Error detection & correction codes: parity checking, even
parity, odd parity, Hamming code.
Boolean theorems and logic operations
Boolean theorems, principle of complementation & duality, De-Morgan theorems. Logic
operations; Basic logic operations -NOT, OR, AND, Universal Logic operations, EX-OR,
EX-NOR operations. Standard SOP and POS Forms, NAND-NAND and NOR-NOR
realizations.
UNIT - II
Minimization Techniques:
Minimization and realization of switching functions using Boolean theorems, K-Map (up to 6
variables) and tabular method.
Combinational Logic Circuits Design:
Design of Half adder, full adder, half subtractor, full subtractor, applications of full adders; 4-
bit adder-subtractor circuit, BCD adder circuit, Excess 3 adder circuit and carry look-a-head
adder circuit
UNIT - III
Combinational Logic Circuits Design Using MSI &LSI:
Design of encoder, decoder, multiplexer and demultiplexers, Implementation of higher order
circuits using lower order circuits. Realization of Boolean functions using decoders and
multiplexers. Design of Priority encoder, 4-bit digital comparator and seven segment decoder
Introduction of PLD’s:
PLDs: PROM, PAL, PLA -Basics structures, realization of Boolean functions.
UNIT - IV
Sequential Circuits-I:
Classification of sequential circuits (synchronous and asynchronous) , operation of NAND
& NOR Latches and flip-flops; truth tables and excitation tables of RS flip-flop, JK flip-
flop, T flip-flop, D flip-flop with reset and clear terminals. Conversion from one flip-flop to
another flip-flop. Design of ripple counters, design of synchronous counters, Johnson
counter, ring counter. Design of registers - Buffer register, control buffer register, shift
register, bi-directional shift register, universal shift register.
UNIT - V
Sequential Circuits -II:
Finite state machine; state diagrams, state tables, reduction of state tables. Analysis of
clocked sequential circuits Mealy to Moore conversion and vice-versa. Realization of
sequence generator and sequence detector circuits, Races and Hazards.
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